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ZC0302 VGA & CIF USB PC Camera Controller
ZC0302
VGA USB PC Camera Processor
Vimicro Corporation
Data Sheet
Vimicro Corporation reserves the right to make changes without further notice to any product herein to improve reliability, function or design. Vimicro does not assume any liability arising out of the application or use of any
project, circuit described herein; neither does it convey any license under its patent nor the right of others. This document contains information of a proprietary nature. None of this information shall be divulged to persons other than Vimicro Corporation employee authorized by the nature of their duties to receive such information, or individuals or organizations authorized by Vimicro Corporation.
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ZC0302 VGA & CIF USB PC Camera Controller
Contents
1. Features 4
1.1. General Features 4 5 5 6 6 6 6 6 6 8 8
2. Architecture
5
2.1. ZC0302 Block Diagram 2.2. CMOS Image Sensor Interfaces 2.3. USB Features 2.4. Image Signal Processing 2.5. Raster 2.6. Compression Engine 2.7. Audio Interface 2.8. System Controller
3. Pin Definition
8 10
10 10 10 11 11 12 12
3.1. Pin Assignment 3.2. Pin Description
4. Electrical Characteristics
4.1. Absolute Maximum Ratings 4.2. DC Characteristics 4.3. USB Transceiver AC Characteristics 4.4. RESET Timing AC Characteristics 4.5. Clock AC Characteristics 4.6. Input Signal AC Characteristics 4.7. Output Signal AC Characteristic
5. Mechanical Information 13 6. Appendix 13
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ZC0302 VGA & CIF USB PC Camera Controller
Illustrations
Figure 1 USB PC Camera System Block Diagram Figure 2 Block diagram of ZC0302 Figure 3 48-Pin LQFP Package Figure 4 RESET Timing AC Characteristics Diagram Figure 5 Clock Timing AC Characteristics Diagram Figure 6. Input signal AC characteristics Figure 7. VSYNC/HSYNC output AC characteristics Figure 8. 48-Pin LQFP Package Diagram (OMITTED) Figure 9. Serial Bus Timing Diagram 3 5 8 11 11 12 12 13 13
Tables
Table 3.1 ZC0302 Pin Descriptions Table 4.1 Absolute Maximum Ratings Table 4.2 DC Characteristics Table 4.3 Full-Speed Driver Electrical Characteristics Table 4.4 Low-Speed Driver Electrical Characteristics Table 4.5 Reset Signal AC Characteristics Table 4.6 Clock Signal AC Characteristics Table 4.7 CS_D input signal AC Characteristics Table 4.8 Vsync / Hsync input AC Characteristics Table 4.9 Vsync / Hsync output AC characteristics Table 5.1 ZC0302 Package Dimension Table 7. Serial Bus Timing Table 8 10 10 10 10 11 11 12 12 13 13 14
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ZC0302 VGA & CIF USB PC Camera Controller
1. Features
EEPROM
ESCK ESDA
VSYNC HSYNC DATA[8:0] PCLK ENB Serial Interface CMOS IMAGE SENSORS
OSCIN OSCOUT CRYSTAL 48M Hz
ZC0302
USB CABLE
PC
MIC
FIGURE 1 USB PC CAMERA SYSTEM BLOCK DIAGRAM The ZC0302 chip provides a cost effective single chip solution for the PC camera application. It communicates with PC host via Universal Serial Bus (USB) port. All major image processing functions, such as image signal processing (ISP), image data compression and data transfer units are built in the chip. Meanwhile ZC0302 also provides high quality audio sampling function for sound recording. The audio function complies with USB audio class 1.0. ZC0302 is designed as a cost-effective single-chip device replacing the complex and costly chip sets used in current PC camera designs with embedded USB device controller and transceiver, 48-QFP package, and no external DRAM requirement. Advanced on-chip image signal processor and JPEG encoder produce images with superior quality.
1.1. General Features
Low cost, single chip solution for high resolution USB PC camera applications Audio function complying to USB audio device class 1.0 Support up to 15 fps VGA video display without DRAM USB Device Controller compliant with USB protocol 1.1 USB parameter configurable through EEPROM Support 9/8-bit RGB Bayer pattern raw data input from CMOS image sensors Support programmable color correction and gamma correction Support programmable Auto Exposure/Auto White Balance Support Auto Gain Control Support ISO/IEC 10918-1 (JPEG) standard image compression Support 4 quantization tables for programmable image quality Support raw data output for high quality still image 3.3V I/O, 2.5V core No external DRAM required Flexible system level solution support
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ZC0302 VGA & CIF USB PC Camera Controller
2. Architecture
2.1. ZC0302 Block Diagram
EEPROM
MIC
CIS (CMOS Image Sensor)
EEPROM Interface
Audio Interface UDC (USB Device Controller)
System Controller CIS Interface
PC HOST
Subsample & Raster
ZC0302
FIGURE 2 BLOCK DIAGRAM OF ZC0302 Figure 2 shows the block diagram of ZC0302. The ISP block receives RGB raw data from CMOS image sensor interface and performs various image processing tasks such as white balance, color correction, gamma correction, histogram equalization and so on. The Sub-sample & Raster block handles the input image data scaling and converts input image data to 8x8 block data format required by DCT module. The JPEG Encoder block compresses the image data from ISP block into JPEG format data. The compressed image data is then transferred to PC host via USB Device Controller (UDC) block for display. The Audio Interface takes the audio input in mono 16-bit PCM format, and then transfers it to PC Host through the audio streaming pipe in UDC.
2.2. CMOS Image Sensor Interfaces
Support sensors from most CMOS image sensor vendors including Agilent, Hynix, IC Media, TASC, PixArt, Photobit, OmniVision, and Century 9bit/8bit camera input interface
JPEG Encoder
ISP
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ZC0302 VGA & CIF USB PC Camera Controller
2.3. USB Features
Built-in USB transceiver Suspend and Remote wakeup 3 interface for video, audio and control Programmable OEM USB parameters by EEPROM including: vendor ID, product ID, MaxPower, serial Number, manufacture descriptor, product descriptor and chip revision.
2.4. Image Signal Processing
Hardware Dead Pixel Detection/Concealment 8/9-bit RGB raw data input from CMOS image sensor 2-wire/3-wire serial bus interface to CMOS image sensor Programmable white balance, color correction and gamma correction Support automatic Exposure Control, automatic White Balance, automatic CMOS Reset Level Control, automatic Gain Control and auto/manual Histogram Equalization Support programmable AE/AWB windows Support edge enhancement and noise removal Support 2x2 Sub-Sampling
2.5. Raster
The output data format is 4:2:2 YCbCr Change the input image data to 8x8 block data format required by the DCT
2.6. Compression Engine
Standard JPEG compression engine comply to ISO/IEC 10918-1 (JPEG) 2 AC and 2 DC Huffman code table 4 quantization tables for different image quality Adjustable compression rate by Bit Rate Control (BRC) engine Simplified JPEG header for better performance are programmable VGA @ 15fps, CIF/SIF up to 30 fps Adjustable frame rate for efficient bandwidth usage
2.7. Audio Interface
Built-in 16-bit mono audio ADC for audio recording through microphone Sampling rate @ 8K/16K Hz USB audio device class 1.0 compliance
2.8. System Controller
Providing the control to ISP, JPEG, and USB blocks Configuring the control registers Chip clock generation
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ZC0302 VGA & CIF USB PC Camera Controller
Error detection and handling through USB interface
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ZC0302 VGA & CIF USB PC Camera Controller
3. Pin Definition
3.1. Pin Assignment
CS_PWDB 38
CS_RSTB
CS_CLK
HSYNC
VSYNC
CS_EN
OVDD
48
47
46
45
44
43
42
41
40
39
CS_D[8] CS_D[7] CS_D[6] CS_D[5] NC NC CS_D[4] CS_D[3] CS_D[2] CS_D[1] CS_D[0] PWUP_RST
37
ESDA
OVSS
SDA
SCK
NC
1 2 3 4 5 6 7 8 9 10 11 12
36 35 34 33
PIO[3] ESCK PIO[2] PIO[1] PIO[0] TEST NC VCM VREFOUT GND_REF MIC VDD_A
ZSMC ZC0302 - 48 LQFP
32 31 30 29 28 27 26 25
13
14
15
16
17
18
19
20
21
22
23 SNAPB
VSS_USB
VDD_USB
DVSS
NC
DP
SUSPENDB
CLKXIN
CLKXOUT
FIGURE 3 48-PIN LQFP PACKAGE
3.2. Pin Description
Pin CS_D[8]
CS_D[7] CS_D[6] CS_D[5]
Type
I, PD I, PD I, PD I, PD
Function
Sensor data Sensor data Sensor data Sensor data
GND_A
DM
DVDD
24
48 Pin LQFP
1 2 3 4
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Mar. 2002
ZC0302 VGA & CIF USB PC Camera Controller
Pin
CS_D[4] CS_D[3] CS_D[2] CS_D[1] CS_D[0] PWUP_RST CLKXIN CLKXOUT DVSS VSS_USB DP DM VDD_USB SUSPENDB DVDD SNAPB GND_A VDD_A MIC GND_REF VREFOUT VCM TEST PIO[0] PIO[1] PIO[2] ESCK PIO[3] ESDA CS_PWDB VSYNC HSYNC OVSS OVSS CS_CLK OVDD SCK / SICLK SDA / SIVAL CS_ENB / SI_EN CS_RSTB / AECNT
Type
I, PD I, PD I, PD I, PD I, PD I, Schmitt I O P P I/O I/O P O P I, PU P P A A A A I, PD I/O, PD I/O, PD I/O, PD O I/O, PD I/O, Schmitt O I/O, PD I/O, PD P P O P O, PD I/O, Schmitt O, PD O, PD
Function
Sensor data Sensor data Sensor data Sensor data Sensor data Power on reset, active low Crystal input Crystal output Core ground USB transceiver ground USB data USB data USB transceiver power Active-low suspend Core power Snapshot and remote wake up, active low IADC analog ground IADC analog power IADC microphone input IADC input ground reference IADC reference voltage IADC common-mode voltage Manufacturing test mode General purpose I/O General purpose I/O General purpose I/O SEEPROM clock General purpose I/O EEPRPOM data Power-down pin controlling DC/DC regulator Vertical synchronous signal Horizontal synchronous signal I/O ground I/O ground Sensor clock I/O power Serial interface clock Serial interface data Sensor power enable / Serial interface enable Sensor reset / auto exposure for TASC VGA sensor
48 Pin LQFP
7 8 9 10 11 12 13 14 15 16 17 18 19 21 22 23 24 25 26 27 28 29 31 32 33 34 35 36 37 38 39 40 41 41 42 43 45 46 47 48
TABLE 3.1 ZC0302 PIN DESCRIPTIONS
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ZC0302 VGA & CIF USB PC Camera Controller
4. Electrical Characteristics
4.1. Absolute Maximum Ratings
Ambient temperature Storage temperature DC supply voltage I/O pin voltage with respect to VSS 0oC to 70oC -40oC to 125oC 3.0V to 3.6V -0.3V to VDD + 0.3V
TABLE 4.1 ABSOLUTE MAXIMUM RATINGS
4.2. DC Characteristics
Symbol
VDD3V VDD2V Vil Vih Vol Voh Ipd Ido
Parameter
3.3V Power Supply 2.5V Power Supply Input Low voltage Input High voltage Output Low Voltage Output High Voltage Suspend current Active current
Conditions
Min
3.0 2.25 -0.5 2.3 2.4 -
Max
3.6 2.75 1.0 5.5 0.4 500 80
Unit
V V V V V V uA mA
TABLE 4.2 DC CHARACTERISTICS
4.3. USB Transceiver AC Characteristics
Symbol
TFR TFF TFRFF
Parameter
Rise time Fall time Rise and fall time matching
Conditions
CL=50p CL=50p TLRLF=TLR/TLF
Min
4 4 90 20 20
Typ
Max
Unit
ns ns %
111.11
TABLE 4.3 FULL-SPEED DRIVER ELECTRICAL CHARACTERISTICS Symbol
TLR TLF
Parameter
Rise time Fall time
Conditions
CL=50p CL=600p CL=50p CL=600p
Min Typ Max
75 300 75 300
Unit
ns ns
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Mar. 2002
ZC0302 VGA & CIF USB PC Camera Controller
TLRLF Rise and fall time matching TLRLF=TLR/TLF 80 125
%
TABLE 4.4 LOW-SPEED DRIVER ELECTRICAL CHARACTERISTICS
4.4. RESET Timing AC Characteristics
FIGURE 4 RESET TIMING AC CHARACTERISTICS DIAGRAM Symbol
Trst
Parameter
Reset Pulse Width
Conditions
Min
--
Max
20
Unit
ms
TABLE 4.5 RESET SIGNAL AC CHARACTERISTICS
4.5. Clock AC Characteristics
FIGURE 5 CLOCK TIMING AC CHARACTERISTICS DIAGRAM Symbol
1/Tcyc Thigh
Parameter
Oscillator Frequency Oscillator Clock High Time
Conditions
48@10PPM
Min
8.3
Max
-
Unit
Mhz Ns
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Mar. 2002
ZC0302 VGA & CIF USB PC Camera Controller
Tlow Oscillator Clock Low Time 8.3 Ns
TABLE 4.6 CLOCK SIGNAL AC CHARACTERISTICS
4.6. Input Signal AC Characteristics
CS_CLK Tsu CS_D Th Valid data
CS_CLK VSYNC/HSYNC
Tsu
Th
FIGURE 6. INPUT SIGNAL AC CHARACTERISTICS
Symbol
Tsu Th
Parameter
Input setup time Input hold time
Conditions
Min
0
Max
45 -
Unit
ns ns
TABLE 4.7 CS_D INPUT SIGNAL AC CHARACTERISTICS Symbol
Tsu Th
parameter
Input setup time Input hold time
conditions
Min
0
Max
20 -
Unit
ns ns
TABLE 4.8 VSYNC / HSYNC INPUT AC CHARACTERISTICS
4.7. Output Signal AC Characteristic
CS_CLK VSYNC/HSYNC Td
FIGURE 7. VSYNC/HSYNC OUTPUT AC CHARACTERISTICS Symbol
Td
Parameter
Output delay
Conditions
Min
-
Max
1.5
Unit
ns
TABLE 4.9 VSYNC/HSYNC OUTPUT AC CHARACTERISTICS
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ZC0302 VGA & CIF USB PC Camera Controller
5. Mechanical Information
FIGURE 8. 48-PIN LQFP PACKAGE DIAGRAM (OMITTED) Lead Count
Body Size Stand-Off Body Thickness Lead Width Lead Thickness Lead Pitch D1 E1 A1 A2 b c e
48
7 7 0.1 1.4 0.2 0.127 0.5
TABLE 5.1 ZC0302 PACKAGE DIMENSION (unit:
mm)
6. Appendix
FIGURE 9. SERIAL BUS TIMING DIAGRAM Parameter
SCK clock frequency Time that I2C bus must be free before a new transmission can start Hold time for a START LOW period of SCK HIGH period of SCK Setup time for START Data hold time Data setup time Rise time of both SDA and SCK Fall time of both SDA and SCK Setup time for STOP Capacitive load of each bus lines (SDA, SCK)
Symbol
fsck tbuf thd;Sta tlow thigh tsu;Sta thd;dat tsu;dat tr tf tsu;Stp Cb
Min
0 4.7 4.0 4.7 4.0 4.7 0 200 4.7 -
Max.
100 1 300 -
Unit
KHz us us us us us us ns us ns us pf
TABLE 7. SERIAL BUS TIMING TABLE
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Mar. 2002

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